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1/38 preliminary data february 2005 this is preliminary information on a new product now in devel opment or undergoing evaluation. de tails are subject to change wit hout notice. m25p64 64 mbit, low voltage, serial flash memory with 50mhz spi bus interface features summary 64mbit of flash memory page program (up to 256 bytes) in 1.4ms (typical) sector erase (512kbit) bulk erase (64mbit) 2.7 to 3.6v single supply voltage spi bus compatible serial interface 50mhz clock rate (maximum) electronic signatures ? jedec standard two-byte signature (2017h) ? res instruction, one-byte, signature (16h), for backward compatibility more than 100000 erase/program cycles per sector more than 20-year data retention figure 1. packages vdfpn8 (me) 8x6mm (mlp8) so16 (mf) 300 mils width
m25p64 2/38 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. vdfpn connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. so connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 chip select (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 hold (hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 write protect (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. bus master and memory devices on the spi bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bp2, bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 srwd bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. write enable (wren) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/38 m25p64 figure 10.write disable (wrdi) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. read identification (rdid) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11.read identification (rdid) instruction sequence and data-out sequence . . . . . . . . . . 16 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 bp2, bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 srwd bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12.read status register (rdsr) instruction sequence and data-out sequence . . . . . . . 17 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. protection modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13.write status register (wrsr) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 read data bytes (read). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14.read data bytes (read) instruction sequence and data-out sequence . . . . . . . . . . . 20 read data bytes at higher speed (fast_read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15.read data bytes at higher speed (fast_read) instruction and data-out sequence 21 page program (pp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 16.page program (pp) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 sector erase (se) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 17.sector erase (se) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 bulk erase (be) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 18.bulk erase (be) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 read electronic signature (res) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 19.read electronic signature (res) instruction sequence and data-out sequence . . . . . 25 power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 figure 20.power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. power-up timing and vwi threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 initial delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 10. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 11. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 21.ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 22.serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 23.write protect setup and hold timing during wrsr when srwd=1 . . . . . . . . . . . . . . . 32 figure 24.hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
m25p64 4/38 figure 25.output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 26.mlp8, 8-lead very thin dual flat package no lead, 8x6mm, package outline . . . . . . . 34 table 15. mlp8, 8-lead very thin dual flat package no lead, 8x6mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 27.so16 wide ? 16 lead plastic small outline, 300 mils body width . . . . . . . . . . . . . . . . . . 35 table 16. so16 wide ? 16 lead plastic small outline, 300 mils body width . . . . . . . . . . . . . . . . . . 35 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5/38 m25p64 summary description the m25p64 is a 64mbit (8m x 8) serial flash memory, with advanced write protection mecha- nisms, accessed by a high speed spi-compatible bus. the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. the memory is organized as 128 sectors, each containing 256 pages. each page is 256 bytes wide. thus, the whole memory can be viewed as consisting of 32768 pages, or 8388608 bytes. the whole memory can be erased using the bulk erase instruction, or a sector at a time, using the sector erase instruction. figure 2. logic diagram table 1. signal names figure 3. vdfpn connections note: 1. there is an exposed die paddle on the underside of the mlp8 package. this is pulled, internally, to v ss , and must not be allowed to be connected to any other voltage or signal line on the pcb. 2. see package mechanical section for package di- mensions, and how to identify pin-1. figure 4. so connections note: 1. du = don?t use 2. see package mechanical section for package di- mensions, and how to identify pin-1. c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground ai07485 s v cc m25p64 hold v ss w q c d 1 ai08595 2 3 4 8 7 6 5 d v ss c hold q sv cc w m25p64 1 ai07486b 2 3 4 16 15 14 13 du du du du v cc hold du du m25p64 5 6 7 8 12 11 10 9 w q v ss du du s d c
m25p64 6/38 signal description serial data output (q). this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). serial data input (d). this input signal is used to transfer data serially into the device. it receives in- structions, addresses, and the data to be pro- grammed. values are latched on the rising edge of serial clock (c). serial clock (c). this input signal provides the timing of the serial interface. instructions, address- es, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select (s ). when this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal pro- gram, erase or write status register cycle is in progress, the device will be in the standby power mode. driving chip select (s ) low selects the de- vice, placing it in the active power mode. after power-up, a falling edge on chip select (s ) is required prior to the start of any instruction. hold (hold ). the hold (hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be se- lected, with chip select (s ) driven low. write protect (w ). the main purpose of this in- put signal is to freeze the size of the area of mem- ory that is protected against program or erase instructions (as specified by the values in the bp2, bp1 and bp0 bits of the status register).
7/38 m25p64 spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from the falling edge of serial clock (c). the difference between the two modes, as shown in figure 6. , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 5. bus master and memory devices on the spi bus note: the write protect (w ) and hold (hold ) signals should be driven, high or low as appropriate. figure 6. spi modes supported ai03746d bus master (st6, st7, st9, st10, others) spi memory device sdo sdi sck cqd s spi memory device cqd s spi memory device cqd s cs3 cs2 cs1 spi interface with (cpol, cpha) = (0, 0) or (1, 1) w hold w hold w hold ai01438b c msb cpha d 0 1 cpol 0 1 q c msb
m25p64 8/38 operating features page programming to program one data byte, two instructions are re- quired: write enable (wren), which is one byte, and a page program (pp) sequence, which con- sists of four bytes plus data. this is followed by the internal program cycle (of duration t pp ). to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be pro- grammed at a time (changing bits from 1 to 0), pro- vided that they lie in consecutive addresses on the same page of memory. sector erase and bulk erase the page program (pp) instruction allows bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved either a sector at a time, using the sector erase (se) instruction, or throughout the entire memory, using the bulk erase (be) instruction. this starts an internal erase cycle (of duration t se or t be ). the erase instruction must be preceded by a write enable (wren) instruction. polling during a write, program or erase cycle a further improvement in the time to write status register (wrsr), program (pp) or erase (se or be) can be achieved by not waiting for the worst case delay (t w , t pp , t se , or t be ). the write in progress (wip) bit is provided in the status regis- ter so that the application program can monitor its value, polling it to establish when the previous write cycle, program cycle or erase cycle is com- plete. active power and standby power modes when chip select (s ) is low, the device is select- ed, and in the active power mode. when chip select (s ) is high, the device is dese- lected, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes in to the standby power mode. the device consumption drops to i cc1 . status register the status register contains a number of status and control bits that can be read or set (as appro- priate) by specific instructions. wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. bp2, bp1, bp0 bits. the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. srwd bit. the status register write disable (srwd) bit is operated in conjunction with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits.
9/38 m25p64 protection modes the environments where non-volatile memory de- vices are used can be very noisy. no spi device can operate correctly in the presence of excessive noise. to help combat this, the m25p64 features the following data protection mechanisms: power on reset and an internal timer (t puw ) can provide protection against inadvertant changes while the power supply is outside the operating specification. program, erase and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion the block protect (bp2, bp1, bp0) bits allow part of the memory to be configured as read- only. this is the software protected mode (spm). the write protect (w ) signal allows the block protect (bp2, bp1, bp0) bits and status register write disable (srwd) bit to be protected. this is the hardware protected mode (hpm). table 2. protected area sizes note: 1. the device is ready to accept a bulk erase instruction if, and only if, all block protect (bp2, bp1, bp0) are 0. status register content memory content bp2 bit bp1 bit bp0 bit protected area unprotected area 0 0 0 none all sectors 1 (128 sectors: 0 to 127) 0 0 1 upper 64th (2 sectors: 126 and 127) lower 63/64ths (126 sectors: 0 to 125) 0 1 0 upper 32nd (4 sectors: 124 to 127) lower 31/32nds (124 sectors: 0 to 123) 0 1 1 upper sixteenth (8 sectors: 120 to 127) lower 15/16ths (120 sectors: 0 to 119) 1 0 0 upper eighth (16 sectors: 112 to 127) lower seven-eighths (112 sectors: 0 to 111) 1 0 1 upper quarter (32 sectors: 96 to 127) lower three-quarters (96 sectors: 0 to 95) 1 1 0 upper half (64 sectors: 64 to 127) lower half (64 sectors: 0 to 63) 1 1 1 all sectors (128 sectors: 0 to 127) none
m25p64 10/38 hold condition the hold (hold ) signal is used to pause any se- rial communications with the device without reset- ting the clocking sequence. however, taking this signal low does not terminate any write status register, program or erase cycle that is currently in progress. to enter the hold condition, the device must be selected, with chip select (s ) low. the hold condition starts on the falling edge of the hold (hold ) signal, provided that this coincides with serial clock (c) being low (as shown in fig- ure 7. ). the hold condition ends on the rising edge of the hold (hold ) signal, provided that this coincides with serial clock (c) being low. if the falling edge does not coincide with serial clock (c) being low, the hold condition starts af- ter serial clock (c) next goes low. similarly, if the rising edge does not coincide with serial clock (c) being low, the hold condition ends after serial clock (c) next goes low. (this is shown in figure 7. ). during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. normally, the device is kept selected, with chip select (s ) driven low, for the whole duration of the hold condition. this is to ensure that the state of the internal logic remains unchanged from the mo- ment of entering the hold condition. if chip select (s ) goes high while the device is in the hold condition, this has the effect of resetting the internal logic of the device. to restart commu- nication with the device, it is necessary to drive hold (hold ) high, and then to drive chip select (s ) low. this prevents the device from going back to the hold condition. figure 7. hold condition activation ai02029d hold c hold condition (standard use) hold condition (non-standard use)
11/38 m25p64 memory organization the memory is organized as: 8388608 bytes (8 bits each) 128 sectors (512kbits, 65536 bytes each) 32768 pages (256 bytes each). each page can be individually programmed (bits are programmed from 1 to 0). the device is sector or bulk erasable (bits are erased from 0 to 1) but not page erasable. figure 8. block diagram ai08520 hold s w control logic high voltage generator i/o shift register address register and counter 256 byte data buffer 256 bytes (page size) x decoder y decoder size of the read-only memory area c d q status register 00000h 7fffffh 000ffh
m25p64 12/38 table 3. memory organization sector address range 127 7f0000h 7fffffh 126 7e0000h 7effffh 125 7d0000h 7dffffh 124 7c0000h 7cffffh 123 7b0000h 7bffffh 122 7a0000h 7affffh 121 790000h 79ffffh 120 780000h 78ffffh 119 770000h 77ffffh 118 760000h 76ffffh 117 750000h 75ffffh 116 740000h 74ffffh 115 730000h 73ffffh 114 720000h 72ffffh 113 710000h 71ffffh 112 700000h 70ffffh 111 6f0000h 6fffffh 110 6e0000h 6effffh 109 6d0000h 6dffffh 108 6c0000h 6cffffh 107 6b0000h 6bffffh 106 6a0000h 6affffh 105 690000h 69ffffh 104 680000h 68ffffh 103 670000h 67ffffh 102 660000h 66ffffh 101 650000h 65ffffh 100 640000h 64ffffh 99 630000h 63ffffh 98 620000h 62ffffh 97 610000h 61ffffh 96 600000h 60ffffh 95 5f0000h 5fffffh 94 5e0000h 5effffh 93 5d0000h 5dffffh 92 5c0000h 5cffffh 91 5b0000h 5bffffh 90 5a0000h 5affffh 89 590000h 59ffffh 88 580000h 58ffffh 87 570000h 57ffffh 86 560000h 56ffffh 85 550000h 55ffffh 84 540000h 54ffffh 83 530000h 53ffffh 82 520000h 52ffffh 81 510000h 51ffffh 80 500000h 50ffffh 79 4f0000h 4fffffh 78 4e0000h 4effffh 77 4d0000h 4dffffh 76 4c0000h 4cffffh 75 4b0000h 4bffffh 74 4a0000h 4affffh 73 490000h 49ffffh 72 480000h 48ffffh 71 470000h 47ffffh 70 460000h 46ffffh 69 450000h 45ffffh 68 440000h 44ffffh 67 430000h 43ffffh 66 420000h 42ffffh 65 410000h 41ffffh 64 400000h 40ffffh 63 3f0000h 3fffffh 62 3e0000h 3effffh 61 3d0000h 3dffffh 60 3c0000h 3cffffh 59 3b0000h 3bffffh 58 3a0000h 3affffh 57 390000h 39ffffh sector address range
13/38 m25p64 56 380000h 38ffffh 55 370000h 37ffffh 54 360000h 36ffffh 53 350000h 35ffffh 52 340000h 34ffffh 51 330000h 33ffffh 50 320000h 32ffffh 49 310000h 31ffffh 48 300000h 30ffffh 47 2f0000h 2fffffh 46 2e0000h 2effffh 45 2d0000h 2dffffh 44 2c0000h 2cffffh 43 2b0000h 2bffffh 42 2a0000h 2affffh 41 290000h 29ffffh 40 280000h 28ffffh 39 270000h 27ffffh 38 260000h 26ffffh 37 250000h 25ffffh 36 240000h 24ffffh 35 230000h 23ffffh 34 220000h 22ffffh 33 210000h 21ffffh 32 200000h 20ffffh 31 1f0000h 1fffffh 30 1e0000h 1effffh 29 1d0000h 1dffffh 28 1c0000h 1cffffh 27 1b0000h 1bffffh 26 1a0000h 1affffh 25 190000h 19ffffh 24 180000h 18ffffh 23 170000h 17ffffh 22 160000h 16ffffh 21 150000h 15ffffh sector address range 20 140000h 14ffffh 19 130000h 13ffffh 18 120000h 12ffffh 17 110000h 11ffffh 16 100000h 10ffffh 15 0f0000h 0fffffh 14 0e0000h 0effffh 13 0d0000h 0dffffh 12 0c0000h 0cffffh 11 0b0000h 0bffffh 10 0a0000h 0affffh 9 090000h 09ffffh 8 080000h 08ffffh 7 070000h 07ffffh 6 060000h 06ffffh 5 050000h 05ffffh 4 040000h 04ffffh 3 030000h 03ffffh 2 020000h 02ffffh 1 010000h 01ffffh 0 000000h 00ffffh sector address range
m25p64 14/38 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (d) is sampled on the first rising edge of serial clock (c) after chip select (s ) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (d), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in table 4. . every instruction sequence starts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), read status register (rdsr), read identification (rdid) or read electronic signature (res) in- struction, the shifted-in instruction sequence is fol- lowed by a data-out sequence. chip select (s ) can be driven high after any bit of the data-out se- quence is being shifted out. in the case of a page program (pp), sector erase (se), bulk erase (be), write status register (wrsr), write enable (wren) or write disable (wrdi), chip select (s ) must be driven high ex- actly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip se- lect (s ) must driven high when the number of clock pulses after chip select (s ) being driven low is an exact multiple of eight. all attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cy- cle continues unaffected. table 4. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 06h 0 0 0 wrdi write disable 0000 0100 04h 0 0 0 rdid read identification 1001 1111 9fh 0 0 1 to 3 rdsr read status register 0000 0101 05h 0 0 1 to wrsr write status register 0000 0001 01h 0 0 1 read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to pp page program 0000 0010 02h 3 0 1 to 256 se sector erase 1101 1000 d8h 3 0 0 be bulk erase 1100 0111 c7h 0 0 0 res read electronic signature 1010 1011 abh 0 3 1 to
15/38 m25p64 write enable (wren) the write enable (wren) instruction ( figure 9. ) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set pri- or to every page program (pp), sector erase (se), bulk erase (be) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by driving chip select (s ) low, sending the in- struction code, and then driving chip select (s ) high. figure 9. write enable (wren) instruction sequence write disable (wrdi) the write disable (wrdi) instruction ( figure 10. ) resets the write enable latch (wel) bit. the write disable (wrdi) instruction is entered by driving chip select (s ) low, sending the instruc- tion code, and then driving chip select (s ) high. the write enable latch (wel) bit is reset under the following conditions: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrsr) instruction completion ? page program (pp) instruction completion ? sector erase (se) instruction completion ? bulk erase (be) instruction completion figure 10. write disable (wrdi) instruction sequence c d ai02281e s q 2 1 34567 high impedance 0 instruction c d ai03750d s q 2 1 34567 high impedance 0 instruction
m25p64 16/38 read identification (rdid) the read identification (rdid) instruction allows the 8-bit manufacturer identification to be read, fol- lowed by two bytes of device identification. the manufacturer identification is assigned by jedec, and has the value 20h for stmicroelectronics. the device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (17h). any read identification (rdid) instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select (s ) low. then, the 8-bit instruction code for the in- struction is shifted in. this is followed by the 24-bit device identification, stored in the memory, being shifted out on serial data output (q), each bit be- ing shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 11. . the read identification (rdid) instruction is termi- nated by driving chip select (s ) high at any time during data output. when chip select (s ) is driven high, the device is put in the standby power mode. once in the standby power mode, the device waits to be se- lected, so that it can receive, decode and execute instructions. table 5. read identification (rdid) data-out sequence figure 11. read identification (rdid) instruction sequence and data-out sequence manufacturer identification device identification memory type memory capacity 20h 20h 17h c d s 2 1 3456789101112131415 instruction 0 ai06809b q manufacturer identification high impedance msb 15 1413 3210 device identification msb 16 17 18 28 29 30 31
17/38 m25p64 read status register (rdsr) the read status register (rdsr) instruction al- lows the status register to be read. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status reg- ister continuously, as shown in figure 12. . table 6. status register format the status and control bits of the status register are as follows: wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. wel bit. the write enable latch (wel) bit indi- cates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register, program or erase instruction is accepted. bp2, bp1, bp0 bits. the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. these bits are written with the write status register (wrsr) in- struction. when one or more of the block protect (bp2, bp1, bp0) bits is set to 1, the relevant mem- ory area (as defined in table 2. ) becomes protect- ed against page program (pp) and sector erase (se) instructions. the block protect (bp2, bp1, bp0) bits can be written provided that the hard- ware protected mode has not been set. the bulk erase (be) instruction is executed if, and only if, all block protect (bp2, bp1, bp0) bits are 0. srwd bit. the status register write disable (srwd) bit is operated in conjunction with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect (w ) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. figure 12. read status register (rdsr) instruction sequence and data-out sequence b7 b0 srwd 0 0 bp2 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit c d s 2 1 3456789101112131415 instruction 0 ai02031e q 7 6543210 status register out high impedance msb 7 6543210 status register out msb 7
m25p64 18/38 write status register (wrsr) the write status register (wrsr) instruction al- lows new values to be written to the status regis- ter. before it can be accepted, a write enable (wren) instruction must previously have been ex- ecuted. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruction is entered by driving chip select (s ) low, followed by the instruction code and the data byte on serial data input (d). the instruction sequence is shown in figure 13. . the write status register (wrsr) instruction has no effect on b6, b5, b1 and b0 of the status reg- ister. b6 and b5 are always read as 0. chip select (s ) must be driven high after the eighth bit of the data byte has been latched in. if not, the write status register (wrsr) instruction is not executed. as soon as chip select (s ) is driv- en high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction al- lows the user to change the values of the block protect (bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as de- fined in table 2. . the write status register (wrsr) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect (w ) signal. the status register write disable (srwd) bit and write protect (w ) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not execut- ed once the hardware protected mode (hpm) is entered. table 7. protection modes note: 1. as defined by the values in the block protect (b p2, bp1, bp0) bits of the stat us register, as shown in table 2. . the protection features of the device are summa- rized in table 7. when the status register write disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) in- struction, regardless of the whether write protect (w ) is driven high or low. when the status register write disable (srwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect (w ): ? if write protect (w ) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. ? if write protect (w ) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are rejected, and are not accepted for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect (bp2, bp1, bp0) bits of the status register, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: w signal srwd bit mode write protection of the status register memory content protected area 1 unprotected area 1 10 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the srwd, bp2, bp1 and bp0 bits can be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions 00 11 01 hardware protected (hpm) status register is hardware write protected the values in the srwd, bp2, bp1 and bp0 bits cannot be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions
19/38 m25p64 ? by setting the status register write disable (srwd) bit after driving write protect (w ) low ? or by driving write protect (w ) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect (w ) high. if write protect (w ) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp2, bp1, bp0) bits of the status register, can be used. figure 13. write status register (wrsr) instruction sequence c d ai02282d s q 2 1 3456789101112131415 high impedance instruction status register in 0 765432 0 1 msb
m25p64 20/38 read data bytes (read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the mem- ory contents, at that address, is shifted out on se- rial data output (q), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (c). the instruction sequence is shown in figure 14. . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shift- ed out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is termi- nated by driving chip select (s ) high. chip select (s ) can be driven high at any time during data out- put. any read data bytes (read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 14. read data bytes (read) instruction sequence and data-out sequence note: 1. address bit a23 is don?t care. c d ai03748d s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 76543 1 7 0 high impedance data out 1 instruction 24-bit address 0 msb msb 2 39 data out 2
21/38 m25p64 read data bytes at higher speed (fast_read) the device is first selected by driving chip select (s ) low. the instruction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 15. . the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shift- ed out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest ad- dress is reached, the address counter rolls over to 000000h, allowing the read sequence to be contin- ued indefinitely. the read data bytes at higher speed (fast_read) instruction is terminated by driving chip select (s ) high. chip select (s ) can be driv- en high at any time during data output. any read data bytes at higher speed (fast_read) in- struction, while an erase, program or write cycle is in progress, is rejected without having any ef- fects on the cycle that is in progress. figure 15. read data bytes at higher speed (fast_read) instruction and data-out sequence note: address bit a23 is don?t care. c d ai04006 s q 23 2 1 345678910 28293031 2221 3210 high impedance instruction 24 bit address 0 c d s q 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35
m25p64 22/38 page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). before it can be accepted, a write enable (wren) instruction must previously have been ex- ecuted. after the write enable (wren) instruction has been decoded, the device sets the write en- able latch (wel). the page program (pp) instruction is entered by driving chip select (s ) low, followed by the in- struction code, three address bytes and at least one data byte on serial data input (d). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 16. . if more than 256 bytes are sent to the device, pre- viously latched data are discarded and the last 256 data bytes are guaranteed to be programmed cor- rectly within the same page. if less than 256 data bytes are sent to device, they are correctly pro- grammed at the requested addresses without hav- ing any effects on the other bytes of the same page. chip select (s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (s ) is driven high, the self- timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page which is protected by the block protect (bp2, bp1, bp0) bits (see table 2. and table 3. ) is not execut- ed. figure 16. page program (pp) instruction sequence c d ai04082b s 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 c d s 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 instruction 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb
23/38 m25p64 sector erase (se) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decod- ed, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (s ) low, followed by the in- struction code, and three address bytes on serial data input (d). any address inside the sector (see table 3. ) is a valid address for the sector erase (se) instruction. chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 17. . chip select (s ) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (s ) is driven high, the self-timed sector erase cycle (whose du- ration is t se ) is initiated. while the sector erase cy- cle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a page which is protected by the block protect (bp2, bp1, bp0) bits (see table 2. and table 3. ) is not execut- ed. figure 17. sector erase (se) instruction sequence note: address bit a23 is don?t care. 24 bit address c d ai03751d s 2 1 3456789 293031 instruction 0 23 22 2 0 1 msb
m25p64 24/38 bulk erase (be) the bulk erase (be) instruction sets all bits to 1 (ffh). before it can be accepted, a write enable (wren) instruction must previously have been ex- ecuted. after the write enable (wren) instruction has been decoded, the device sets the write en- able latch (wel). the bulk erase (be) instruction is entered by driv- ing chip select (s ) low, followed by the instruction code on serial data input (d). chip select (s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 18. . chip select (s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the bulk erase instruction is not exe- cuted. as soon as chip select (s ) is driven high, the self-timed bulk erase cycle (whose duration is t be ) is initiated. while the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed bulk erase cycle, and is 0 when it is com- pleted. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the bulk erase (be) instruction is executed only if all block protect (bp2, bp1, bp0) bits are 0. the bulk erase (be) instruction is ignored if one, or more, sectors are protected. figure 18. bulk erase (be) instruction sequence c d ai03752d s 2 1 34567 0 instruction
25/38 m25p64 read electronic signature (res) the instruction is used to read, on serial data out- put (q), the old-style 8-bit electronic signature, whose value for the m25p64 is 16h . please note that this is not the same as, or even a subset of, the jedec 16-bit electronic signature that is read by the read identifier (rdid) instruc- tion. the old-style electronic signature is support- ed for reasons of backward compatibility, only, and should not be used for new designs. new designs should, instead, make use of the jedec 16-bit electronic signature, and the read identifier (rdid) instruction. the device is first selected by driving chip select (s ) low. the instruction code is followed by 3 dummy bytes, each bit being latched-in on serial data input (d) during the rising edge of serial clock (c). then, the old-style 8-bit electronic sig- nature, stored in the memory, is shifted out on se- rial data output (q), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 19. the read electronic signature (res) instruction is terminated by driving chip select (s ) high after the electronic signature has been read at least once. sending additional clock cycles on serial clock (c), while chip select (s ) is driven low, cause the electronic signature to be output re- peatedly. when chip select (s ) is driven high, the device is put in the standby power mode. once in the standby power mode, the device waits to be se- lected, so that it can receive, decode and execute instructions. driving chip select (s ) high after the 8 - bit instruc- tion byte has been received by the device, but be- fore the whole of the 8-bit electronic signature has been transmitted for the first time, still ensures that the device is put into standby power mode. once in the standby power mode, the device waits to be selected, so that it can receive, decode and exe- cute instructions. figure 19. read electronic signature (res) instruction sequence and data-out sequence note: the value of the 8-bit electronic signature, for the m25p64, is 16h. c d ai04047c s q 23 2 1 345678910 2829303132333435 2221 3210 36 37 38 765432 0 1 high impedance electronic signature out instruction 3 dummy bytes 0 msb msb
m25p64 26/38 power-up and power-down at power-up and power-down, the device must not be selected (that is chip select (s ) must follow the voltage applied on v cc ) until v cc reaches the correct value: ?v cc (min) at power-up, and then for a further delay of t vsl ?v ss at power-down usually a simple pull-up resistor on chip select (s ) can be used to ensure safe and proper power-up and power-down. to avoid data corruption and inadvertent write op- erations during power-up, a power on reset (por) circuit is included. the logic inside the de- vice is held reset while v cc is less than the power on reset (por) threshold voltage, v wi ? all oper- ations are disabled, and the device does not re- spond to any instruction. moreover, the device ignores all write enable (wren), page program (pp), sector erase (se), bulk erase (be) and write status register (wrsr) instructions until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold. however, the correct operation of the device is not guaranteed if, by this time, v cc is still below v cc (min). no write status register, program or erase instructions should be sent until the later of: ?t puw after v cc passed the v wi threshold ?t vsl after v cc passed the v cc (min) level these values are specified in table 8. . if the delay, t vsl , has elapsed, after v cc has risen above v cc (min), the device can be selected for read instructions even if the t puw delay is not yet fully elapsed. at power-up, the device is in the following state: ? the device is in the standby power mode ? the write enable latch (wel) bit is reset. normal precautions must be taken for supply rail decoupling, to stabilize the v cc supply. each de- vice in a system should have the v cc rail decou- pled by a suitable capacitor close to the package pins. (generally, this capacitor is of the order of 0.1f). at power-down, when v cc drops from the operat- ing voltage, to below the power on reset (por) threshold voltage, v wi , all operations are disabled and the device does not respond to any instruc- tion. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycle is in progress, some data corruption can result.) figure 20. power-up timing v cc ai04009c v cc (min) v wi reset state of the device chip selection not allowed program, erase and write commands are rejected by the device tvsl tpuw time read access allowed device fully accessible v cc (max)
27/38 m25p64 table 8. power-up timing and v wi threshold note: 1. these parameters are characterized only. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). symbol parameter min. max. unit t vsl (1) v cc (min) to s low 30 s t puw (1) time delay to write instruction 1 10 ms v wi (1) write inhibit voltage 1.5 2.5 v
m25p64 28/38 maximum rating stressing the device outside the ratings listed in table 9. may cause permanent damage to the de- vice. these are stress ratings only, and operation of the device at these, or any other conditions out- side those indicated in the operating sections of this specification, is not implied. exposure to ab- solute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 9. absolute maximum ratings note: 1. compliant with jedec std j-std-020c (for small body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) c v io input and output voltage (with respect to ground) ?0.5 4.0 v v cc supply voltage ?0.2 4.0 v v esd electrostatic discharge voltage (human body model) 2 ?2000 2000 v
29/38 m25p64 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 10. operating conditions table 11. ac measurement conditions note: output hi-z is defined as the point where data out is no longer driven. figure 21. ac measurement i/o waveform table 12. capacitance note: sampled only, not 100% tested, at t a =25c and a frequency of 20 mhz. symbol parameter min. max. unit v cc supply voltage 2.7 3.6 v t a ambient operating temperature ?40 85 c symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input timing reference voltages 0.3v cc to 0.7v cc v output timing reference voltages v cc / 2 v symbol parameter test condition min . max . unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (other pins) v in = 0v 6 pf ai07455 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels 0.5v cc
m25p64 30/38 table 13. dc characteristics symbol parameter test condition (in addition to those in table 10. ) min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current s = v cc , v in = v ss or v cc 50 a i cc3 operating current (read) c=0.1v cc / 0.9.v cc at 50mhz, q = open 8ma c=0.1v cc / 0.9.v cc at 20mhz, q = open 4ma i cc4 operating current (pp) s = v cc 15 ma i cc5 operating current (wrsr) s = v cc 20 ma i cc6 operating current (se) s = v cc 20 ma i cc7 operating current (be) s = v cc 20 ma v il input low voltage ? 0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.2 v v ol output low voltage i ol = 1.6ma 0.4 v v oh output high voltage i oh = ?100 av cc ?0.2 v
31/38 m25p64 table 14. ac characteristics note: 1. t ch + t cl must be greater than or equal to 1/ f c (max) 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a wr sr instruction when srwd is set at 1. test conditions specified in table 10. and table 11. symbol alt. parameter min. typ. max. unit f c f c clock frequency for the following instructions: fast_read, pp, se, be, res, wren, wrdi, rdid, rdsr, wrsr d.c. 50 mhz f r clock frequency for read instructions d.c. 20 mhz t ch (1) t clh clock high time 9 ns t cl (1) t cll clock low time 9 ns t clch (2) clock rise time 3 (peak to peak) 0.1 v/ns t chcl (2) clock fall time 3 (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 5 ns t chsl s not active hold time (relative to c) 5 ns t dvch t dsu data in setup time 2 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup time (relative to c) 5 ns t shsl t csh s deselect time 100 ns t shqz (2) t dis output disable time 8 ns t clqv t v clock low to output valid 8 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 5 ns t chhh hold hold time (relative to c) 5 ns t hhch hold setup time (relative to c) 5 ns t chhl hold hold time (relative to c) 5 ns t hhqx (2) t lz hold to output low-z 8 ns t hlqz (2) t hz hold to output high-z 8 ns t whsl (4) write protect setup time 20 ns t shwl (4) write protect hold time 100 ns t w write status register cycle time 5 15 ms t pp page program cycle time 1.4 5 ms t se sector erase cycle time 1 3 s t be bulk erase cycle time 68 160 s
m25p64 32/38 figure 22. serial input timing figure 23. write protect setup and hold timing during wrsr when srwd=1 c d ai01447c s msb in q tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl c d s q high impedance w twhsl tshwl ai07439
33/38 m25p64 figure 24. hold timing figure 25. output timing c q ai02032 s d hold tchhl thlch thhch tchhh thhqx thlqz c q ai01449e s lsb out d addr.lsb in tshqz tch tcl tqlqh tqhql tclqx tclqv tclqx tclqv
m25p64 34/38 package mechanical figure 26. mlp8, 8-lead very thin dual flat package no lead, 8x6mm, package outline note: drawing is not to scale. table 15. mlp8, 8-lead very thin dual flat package no lead, 8x6mm, package mechanical data symbol millimeters inches typ. min. max. typ. min. max. a 0.85 1.00 0.0335 0.0394 a1 0.00 0.05 0.0000 0.0020 b 0.40 0.35 0.48 0.0157 0.0138 0.0189 d 8.00 0.3150 d2 6.40 0.2520 ddd 0.05 0.0020 e 6.00 0.2362 e2 4.80 0.1890 e 1.27 ? ? 0.0500 ? ? k0.20 0.0079 l 0.50 0.45 0.60 0.0197 0.0177 0.0236 l1 0.15 0.0059 n8 8 d e vdfpn-02 a e e2 d2 l b l1 a1 ddd
35/38 m25p64 figure 27. so16 wide ? 16 lead plastic small outline, 300 mils body width note: drawing is not to scale. table 16. so16 wide ? 16 lead plastic small outline, 300 mils body width symbol millimeters inches typ min max typ min max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 10.10 10.50 0.398 0.413 e 7.40 7.60 0.291 0.299 e 1.27 ? ? 0.050 ? ? h 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.40 1.27 0.016 0.050 0 8 0 8 ddd 0.10 0.004 e 16 d c h 1 8 9 so-h l a1 a ddd a2 b e h x 45?
m25p64 36/38 part numbering table 17. ordering information scheme for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales of- fice. example: m25p64 ? v mf 6 t p device type m25p = serial flash memory for code storage device function 64 = 64mbit (8m x 8) operating voltage v = v cc = 2.7 to 3.6v package mf = so16 (300 mil width) me = vdfpn8 8x6mm (mlp8) device grade 6 = industrial temperature range, ?40 to 85 c. device tested with standard test flow option blank = standard packing t = tape and reel packing plating technology blank = standard snpb plating p or g = rohs compliant
37/38 m25p64 revision history table 18. document revision history date rev. description of revision 28-apr-2003 0.1 target specification document written in brief form 15-may-2003 0.2 target specification document written in full 20-jun-2003 0.3 8x6 mlp8 and so16(300 mil) packages added 18-jul-2003 0.4 t pp , t se and t be revised 02-sep-2003 0.5 voltage supply range changed 19-sep-2003 0.6 table of contents, warning about exposed paddle on mlp8, and pb-free options added 17-dec-2003 0.7 value of t vsl (min) v wi , t pp (typ) and t be (typ) changed. mlp8 package removed. 15-nov-2004 1.0 document status promoted from target specification to preliminary data. 8x6 mlp8 package added. minor wording changes. 24-feb-2005 2.0 deep power-down mode removed from datasheet ( figure 19., read electronic signature (res) instruction sequence and data-out sequence modified and tres1 and tres2 removed from table 14., ac characteristics ). so16 wide package specifications updated. end timing line of t shqz modified in figure 25., output timing . figures moved below the corresponding instructions in the instructions section.
m25p64 38/38 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. ecopack is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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